Infineon Technologies Regensburg
Semiconductor manufacturing is a race for productivity, cycle time. The SMART Fab approach pillars give an opportunity to improve both. This reduces the effort in Fab operations as well as increase the utilization and the optimized loading of the tools and the balancing within the FAB. Especially the introduction of real time scheduling precise the decisions about the next load or batch to run on the tool.
This will cause in various areas an optimized dispatching in at the end better use of the equipment availability. Beside that new opportunities rising up to improve the productivity and the CT further. Using machine-learning methods will support this. This can create a methodology for dynamic dispatching as well as condition-based maintenance or predictive. The boundary condition for these is certainly and optimized logistics workflow with automated delivery and identification of the lots. By using an automated transportation system with an direct delivery to the tool there is an big step towards the CT improvement. It allows to move automated and integrated beside the production lots also the requalification or engineering lots.
With the help of the simulation, either short term or midterm the decision making about optimized loading can be improved or the scheduling of maintenance task can be better introduced in comparison to the operational performance. In total the implementation of the SMART Fab pillars will improve the productivity and operational performance further.
Joerg Recklies has been in the semiconductor industry for 24 years with responsibilities ranging from Chip design to IDM. He is currently in charge of the General Manager at Infineon Technologies Regensburg.
Prior to that, Joerg Recklies was in charge of the FAB Manager at Infineon Dresden and held several positions in Automation and Productions at Infineon. These positions contributed to his excellent experience in terms of equipment and automation. Earlier in his carreer he has made contributions in digital and analog chip design.
Joerg Recklies holds a graduate engineer for Semiconductor.